States of a SRAM Cell

The increasing market demand for ever smaller and application packed portable electronic devices has been fueling the relentless scaling of the CMOS transistor. The ITRS roadmap envisages that high performance CMOS circuits will require ultra-low gate oxide thickness to overcome the effects of shorter channel lengths. However, such devices will be susceptible to a more profound leakage mechanism due to carrier tunneling through the gate oxide. Consequently, the gate oxide tunneling current has emerged as the major component of the leakage power consumption of nanoscale CMOS devices. In the case of an important CMOS circuit like Static RAM (SRAM) there is a high probability for the leakage currents to be manifested with more prominence. SRAMs form a vital component of the CPU cache therefore there is a critical need for analysis, explanation, and characterization of the various tunneling mechanisms SRAMs. This paper explores the gate leakage current scenarios in the READ, WRITE and IDLE states of the SRAM which can make significant contribution to modeling and reduction of gate leakage in SRAM circuits.