The effect of code reordering on branch prediction

Branch prediction accuracy is a very important factor for superscalar processor performance. The ability to pre-dict the outcome of a branch allows the processor to effec-tively use a large instruction window, and extract a larger amount of Instruction Level Parallelism (ILP). In this paper we will examine the effect of code layout op-timizations on branch prediction accuracy and final proces-sor performance. These code reordering techniques align branches so that they tend to be not taken, achieving bet-ter instruction cache performance and increasing the fetch bandwidth. Here we focus on how these optimizations affect both static and dynamic branch prediction. Code reordering mainly increases the number of not tak-en branches, which benefits simple static predictors, whic