Add to ORKGAbstract Delay, power, skew, area, and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power, and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast, and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power d...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
The timing performance of clock trees in scaled technology nodes may be severely degraded by on-chip...
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergenc...
Cloc distribution iscvV(Nj for timing and designcsi vergenc in high-performanc very largescVN i...
jltsaiocae. wisc. edu Abstract- Zero-skew clock-tree.with minimum clock-delay is preferable due to i...
Clock skew constraint satisfaction is one of the most important tasks in the clock network design, e...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...
Abstract — This paper considers simultaneous gate and wire sizing for general very large scale integ...
In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role on d...
Abstract — This paper investigates methods for minimizing the impact of process variation on clock s...
With the growth in chip size and reduction in line width, delays in driving long lines have become i...
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power d...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
The timing performance of clock trees in scaled technology nodes may be severely degraded by on-chip...
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergenc...
Cloc distribution iscvV(Nj for timing and designcsi vergenc in high-performanc very largescVN i...
jltsaiocae. wisc. edu Abstract- Zero-skew clock-tree.with minimum clock-delay is preferable due to i...
Clock skew constraint satisfaction is one of the most important tasks in the clock network design, e...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...
[[abstract]]In synchronous circuit designs, clock skew is difficult to minimize because a single phy...
In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...
Abstract — This paper considers simultaneous gate and wire sizing for general very large scale integ...
In ultra-deep submicron VLSI designs, clock network layout plays an increasingly important role on d...
Abstract — This paper investigates methods for minimizing the impact of process variation on clock s...
With the growth in chip size and reduction in line width, delays in driving long lines have become i...
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power d...
In this thesis, an optimization framework is proposed to synthesize clock trees with useful skews. T...
The timing performance of clock trees in scaled technology nodes may be severely degraded by on-chip...