This paper describes a new recon�gurable processor ar� chitecture called REMARC �Recon�gurable Multime� dia Array Coprocessor�. REMARC is a recon�gurable coprocessor that is tightly coupled to a main RISC pro� cessor and consists of a global control unit and 64 pro� grammable logic blocks called nano processors. RE� MARC is designed to accelerate multimedia applica� tions � such as video compression � decompression � and image processing. These applications typically use 8� bit or 16�bit data therefore � each nano processor has a 16�bit datapath that is much wider than those of other recon�gurable coprocessors. We have developed a pro� gramming environment for REMARC and several real� istic application programs � DES encryption � MPEG�2 dec...
International audienceThe development of more processing demanding applications on the Internet (vid...
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-...
Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platform...
By using an array processor methodology, a reconfigurable processor ReMAP architecture was proposed,...
In this dissertation, we address high performance media processing based on a tightly coupled co-pro...
This paper presents a structured application design trajectory to transform media-processing applica...
Current IC design, especially that for multimedia processing, requires high performance and short de...
Flexibility and high efficiency are common design drivers in the embedded systems domain. Coarse-gr...
In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targe...
The subject of this work is the design and the implementation of hardware components which can accel...
In this paper, a reconfigurable computing processor core for multimedia system-on-chip (SOC) applica...
A new reconfigurable architectural template is presented. Such a template is composed of coarse-grai...
International audienceImage processing applications need embedded devices that can integrate evoluti...
International audienceIn multimedia applications, video and image processing is one of the challenge...
ISBN : 2-84813-091-1During the last years, the chip's complexity increased exponentially. The possib...
International audienceThe development of more processing demanding applications on the Internet (vid...
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-...
Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platform...
By using an array processor methodology, a reconfigurable processor ReMAP architecture was proposed,...
In this dissertation, we address high performance media processing based on a tightly coupled co-pro...
This paper presents a structured application design trajectory to transform media-processing applica...
Current IC design, especially that for multimedia processing, requires high performance and short de...
Flexibility and high efficiency are common design drivers in the embedded systems domain. Coarse-gr...
In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targe...
The subject of this work is the design and the implementation of hardware components which can accel...
In this paper, a reconfigurable computing processor core for multimedia system-on-chip (SOC) applica...
A new reconfigurable architectural template is presented. Such a template is composed of coarse-grai...
International audienceImage processing applications need embedded devices that can integrate evoluti...
International audienceIn multimedia applications, video and image processing is one of the challenge...
ISBN : 2-84813-091-1During the last years, the chip's complexity increased exponentially. The possib...
International audienceThe development of more processing demanding applications on the Internet (vid...
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-...
Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platform...