Reconfigurable Hardware Network Packet Scanning Structure Abstract

Denial-of-service attacks are an increasing problem in today’s networks. Embedded security systems are required as purely software defences are unable to cope with packet rates on highspeed networks. Reconfigurable logic is well suited to the changing nature of the threat. This paper introduces a packet-scanning structure that can be applied to a range of development boards and target systems. Multiple clock domains allow the network interface to be decoupled from the security logic. The design has been accomplished through hardware compilation on a platform FPGA, a method appropriate to quickly matching changing threats. Automatic re-timing offers a way to optimize clock widths. Results show that this is a scalable solution. 1