h Processor for a High-Performance Personal Computer

This paper describes the design goals, micro-architecture. and implementation of the microprogrammed processor for a compact high performance personal com-puter. This computer supports a range of high level tang uage environments and high bandwidth I/O devices. Besides the processor, it has a cache, a memory map, main storage, and an instruction fetch unit; these are described in other papers. The processor can be shared among 16 microcoded tasks, performing microcode context switches on demand vviih essentially no overhead. Conditional branches are done without any lookahead or delay. Micro-instructions are fairly tightly encoded, and use an interes-ting variant on control lield sharing. The processor imple-ments a large number of internal registers, hardware stacks, a cyclic shifter/masker, and an arithmetic/logic unit,!ogether with external data paths for instruction fetching, memory interface, and l/O, in a compact, pipe-lined organization. The machine has a 50 ns microcyclc. and can execute a simple macroinstruction in one cycle: the available I/O bandwidth is 640 Mbits/set. The entire machine, including disk, display and network interfaces, is implemented with approximately 3000 MSI components, mostly ECI, 10K; the processor is about 35 % of this. In addition there are up to-1 storage modules, each with about 300 16K or 64K RhMs and 200 ~1 % components, for a total of 8 Mbytes. Several prototypes are currently running. 1