Abstract DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design

Building a high-petformance microprocessor presents many reliability challenges. Designers must verify the cor-rectness of large complex systems and construct implemen-tations that work reliably in varied (and occasionally ad-verse) operating conditions. To&rther complicate this task, deep submicron fabrication technologies present new relia-bility challenges in the form of degraded signal quality and logic failures caused by natural radiation interference. In this paper; we introduce dynamic verification, a novel microarchitectural technique that can significantly reduce the burden of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. Thefunc-tional checker verifies the correctness of the core proces-sor’s computation, only permitting correct results to com-mit. Overall design cost can be dramatically reduced be-cause designers need only veri ’ the correctness of the checker unit. We detail the DIVA checker architecture, a design opti-mized for simplicity and low cost. Using detailed timing simulation, we show that even resource-frugal DIVA check-ers have little impact on core processor peflormance. To make the case for reduced verification costs, we argue that the DIVA checker should lend itself to functional and elec-trical verification better than a complex core processor Fi-nally, future applications that leverage dynamic veri@cation to increase processor performance and availability are sug-gested.