Reducing Multithreaded Frame Cache Miss Ratio by

ABSTRACT In software-oriented multithread-ing execution model, the compiler identifies the re-mote accesses and performs fast context switches t,o hide remote =cess latency. In TAM model of execu-tion, threads access the local memory through a data structure called “frame”. This paper introduces a cache memory for frame structure and applies two techniques to reduce the cache miss ratio. One is a frame prefetching, which is based on the frame scheduling information, and the other is a changing frame execution sequences by the working frame set concept. Multithreading simulation is performed us-ing benchmark programs and causes of cache misses are classified and analyzed. This paper shows the promising result that the frame prefetching based on scheduling information is very effective to reduce the cache miss ratio. But the effect of reordering the sequence of the frame execution is not so big than the prefetching.