Abstract. Power consumption becomes an important issue for modern processors. The off-chip buses consume considerable amount of total power [9,7]. One effective way to reduce power is to reduce the overall bus switching activities since they are proportional to the power. Up till now, the most effective technique in reducing the switching activities on the data buses is Frequent Value Encoding (FVE) that exploits abundant frequent value locality on the off-chip data buses. In this paper, we propose a technique that exploits more value locality that was overlooked by the FVE. We found that a significant amount of non-frequent values, not captured by the FVE, share common highordered bits. Therefore, we propose to extend the current FVE schem...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
External buses consume substantial power for their high capacitances of bus lines and I/O pins. In t...
Power dissipation is an important design constraint in today’s CMOS VLSI design and is addressed wid...
In the profound submicron innovation area, the on chip buses devour extensive measure of aggregate e...
The need in low power processor design is growing due to the reliability problem for high frequency,...
In microprocessor-based systems, large power savings can be achieved through reduction of the transi...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor...
The dynamic power management (DPM) represents an important challenge for extending the battery lifet...
The power dissipated by system-level buses is the largest contribution to the global power of comple...
To transfer a small number, we inherently need a small number of bits. However all bit lines on a da...
The energy consumption at the I/O pins is a significant part of the overall chip consumption. This p...
The power dissipated by system-level buses is the largest contribution to the global power of compl...
In this paper, we introduce a class of irredundant low power encoding techniques for memory address ...
We explore the possibility of reducing energy consumed by on-chip buses via stateful and stateless c...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
External buses consume substantial power for their high capacitances of bus lines and I/O pins. In t...
Power dissipation is an important design constraint in today’s CMOS VLSI design and is addressed wid...
In the profound submicron innovation area, the on chip buses devour extensive measure of aggregate e...
The need in low power processor design is growing due to the reliability problem for high frequency,...
In microprocessor-based systems, large power savings can be achieved through reduction of the transi...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor...
The dynamic power management (DPM) represents an important challenge for extending the battery lifet...
The power dissipated by system-level buses is the largest contribution to the global power of comple...
To transfer a small number, we inherently need a small number of bits. However all bit lines on a da...
The energy consumption at the I/O pins is a significant part of the overall chip consumption. This p...
The power dissipated by system-level buses is the largest contribution to the global power of compl...
In this paper, we introduce a class of irredundant low power encoding techniques for memory address ...
We explore the possibility of reducing energy consumed by on-chip buses via stateful and stateless c...
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total...
External buses consume substantial power for their high capacitances of bus lines and I/O pins. In t...
Power dissipation is an important design constraint in today’s CMOS VLSI design and is addressed wid...