Add to ORKGIn this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions. We have applied the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip andHSPICE simulations show that our algorithms canreduceskew and power by a factor of 3 5X and 1 6X , respectively, when compared to the manual layout of the clock nets in the original chip
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
This paper first presents an accurate and efficient method of estimating the short circuit energy di...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective f...
An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments...
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We defin...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
Cloc distribution iscvV(Nj for timing and designcsi vergenc in high-performanc very largescVN i...
Abstract: This paper considers the problem of interconnect wire delay in digital integrated circuits...
Abstract — This paper considers simultaneous gate and wire sizing for general very large scale integ...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...
Efficient, generalized delay and power equations are proposed for large scale CMOS circuit analysis ...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergenc...
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
This paper first presents an accurate and efficient method of estimating the short circuit energy di...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective f...
An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments...
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We defin...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
Cloc distribution iscvV(Nj for timing and designcsi vergenc in high-performanc very largescVN i...
Abstract: This paper considers the problem of interconnect wire delay in digital integrated circuits...
Abstract — This paper considers simultaneous gate and wire sizing for general very large scale integ...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...
Efficient, generalized delay and power equations are proposed for large scale CMOS circuit analysis ...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...
As the continuous trend of Very Large Scale Integration (VLSI) circuits technol-ogy scaling and freq...
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergenc...
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
This paper first presents an accurate and efficient method of estimating the short circuit energy di...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...