We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use additional forces to reduce cell overlaps and to consider the placement area. Compared to existing approaches, the main advantage is that the algorithm provides increased flexibility and enables a variety of demanding applications. Our algorithm is capable of addressing the problems of global placement, floorplanning, timing minimization and interaction to logic synthesis. Among the considered objective functions are area, timing, congestion and heat distribution. The iterative nature of the algorithm assures that timing requirements are precisely met. While showing similar CPU time requirements it outperforms Gordian by a...
International audienceLegalization is one of the most critical steps in modern placement designs. Si...
Recently, floorplanning problems become more complex since they need to consider standard cells, mix...
Abstract — The rapid increase in IC design complexity and wide-spread use of intellectual-property (...
We represent a timing driven floorplanning program for general cell layouts. The approach used combi...
In this article we propose an effective algorithm flow to handle modern large-scale mixed-size place...
We present a timing driven floorplanning program for general cell layouts. The approach used combine...
Traditionally, analytic placement used linear or quadratic wirelength objective functions. Minimizin...
In this paper we present a novel force-directed placement algorithm, which is used to solve macro-ce...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...
I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, includ...
The placement of cells in Integrated Circuit Design Automation has a major influence on overall desi...
VLSI physical design automation plays a vital role as we move to deep sub-micron designs below 0.18 ...
A linear wirelength objective more effectively captures timing, congestion, and other global placeme...
The placement step in VLSI physical design flow deals with the problem of determining the locations ...
International audienceLegalization is one of the most critical steps in modern placement designs. Si...
Recently, floorplanning problems become more complex since they need to consider standard cells, mix...
Abstract — The rapid increase in IC design complexity and wide-spread use of intellectual-property (...
We represent a timing driven floorplanning program for general cell layouts. The approach used combi...
In this article we propose an effective algorithm flow to handle modern large-scale mixed-size place...
We present a timing driven floorplanning program for general cell layouts. The approach used combine...
Traditionally, analytic placement used linear or quadratic wirelength objective functions. Minimizin...
In this paper we present a novel force-directed placement algorithm, which is used to solve macro-ce...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...
[[abstract]]We propose a performance-driven cell placement method based on a modified force-directed...
I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, includ...
The placement of cells in Integrated Circuit Design Automation has a major influence on overall desi...
VLSI physical design automation plays a vital role as we move to deep sub-micron designs below 0.18 ...
A linear wirelength objective more effectively captures timing, congestion, and other global placeme...
The placement step in VLSI physical design flow deals with the problem of determining the locations ...
International audienceLegalization is one of the most critical steps in modern placement designs. Si...
Recently, floorplanning problems become more complex since they need to consider standard cells, mix...
Abstract — The rapid increase in IC design complexity and wide-spread use of intellectual-property (...