Given a Directed Acyclic Graph and different possible implementations for each node, the Implementation Selection Problem(ISP) selects the appropriate implementation for each node such that a given global design objective is optimized. ISP is a generic formulation that is explicitly or implicitly solved in several design automation problems like leakage optimization using dual Vth , gate sizing, etc. An implementation of a node results in an associated delay and perhaps cost for the node. In the presence of different sources of uncertainty and fabrication variability, fixed estimates of delays and costs of a node are extremely erroneous. In this paper we investigate a probabilistic approach to solve ISP by considering Probability Density Fu...
Aggressive device scaling has made it imperative to account for process variations in the design flo...
textAs device geometries shrink, variability of process parameters becomes pronounced, resulting in ...
Abstract — Process variations cause design performance to become unpredictable in deep sub-micron te...
VLSI design optimization requires evaluation of di#erent solutions, to compare superiority of one ov...
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for ...
This paper presents a novel gate sizing methodology to mini-mize the leakage power in the presence o...
Today's IC design is facing several challenges due to increasing circuit complexity and decreasing f...
DoctorAs technology node shrinks, process variation (PV) becomes a major concern in circuit design. ...
Abstract-The growing demand in the multimedia rich applications are motivating the low-power and hig...
DoctorAggressive technology scaling makes the process variations a significant problem in VLSI desig...
As the technology scales, there is a need to develop design and optimization algorithms under variou...
Process variations result in a considerable spread in the frequency of the fabricated chips. In high...
One of the main challenges for design in the presence of process variations is to cope with the unce...
With the increased significance of leakage power and performance variability, the yield of a design ...
Vita.This dissertation deals with both theoretical and practical aspects of integrated circuits (IC'...
Aggressive device scaling has made it imperative to account for process variations in the design flo...
textAs device geometries shrink, variability of process parameters becomes pronounced, resulting in ...
Abstract — Process variations cause design performance to become unpredictable in deep sub-micron te...
VLSI design optimization requires evaluation of di#erent solutions, to compare superiority of one ov...
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for ...
This paper presents a novel gate sizing methodology to mini-mize the leakage power in the presence o...
Today's IC design is facing several challenges due to increasing circuit complexity and decreasing f...
DoctorAs technology node shrinks, process variation (PV) becomes a major concern in circuit design. ...
Abstract-The growing demand in the multimedia rich applications are motivating the low-power and hig...
DoctorAggressive technology scaling makes the process variations a significant problem in VLSI desig...
As the technology scales, there is a need to develop design and optimization algorithms under variou...
Process variations result in a considerable spread in the frequency of the fabricated chips. In high...
One of the main challenges for design in the presence of process variations is to cope with the unce...
With the increased significance of leakage power and performance variability, the yield of a design ...
Vita.This dissertation deals with both theoretical and practical aspects of integrated circuits (IC'...
Aggressive device scaling has made it imperative to account for process variations in the design flo...
textAs device geometries shrink, variability of process parameters becomes pronounced, resulting in ...
Abstract — Process variations cause design performance to become unpredictable in deep sub-micron te...