Add to ORKGBy abstracting the details of the data representations and operations in a microprocessor, term-level verification can formally prove that a pipelined microprocessor faithfully implements its sequential, instruction-set architecture specification. Previous efforts in this area have focused on reduced instruction set computer (RISC) and very-large instruction word (VLIW) processors. This work report
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
The paper presents the application of formal verification techniques to a real microprocessor. The d...
By abstracting the details of the data representations and operations in a microprocessor, term-leve...
Abstract. This paper presents status results of a microprocessor verification project. The authors v...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2...
RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in mu...
Abstract — In this paper, we propose a verification method for pipelined microprocessors with out-of...
In this paper a practical methodology for formally verifying RISC cores is presented. This methodolo...
Designing a microprocessor is a significant undertaking. Modern RISC processors are no exception. A...
his article describes a formal approach to the specification and verif ication of a microprocessor d...
In microprocessors, achieving an efficient utilization of the execution units is a key factor in imp...
Abstract- As the complexity of high-performance microprocessor increases, functional verification be...
The Verification methodology of modern processor designs is an enormous challenge. As processor desi...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
The paper presents the application of formal verification techniques to a real microprocessor. The d...
By abstracting the details of the data representations and operations in a microprocessor, term-leve...
Abstract. This paper presents status results of a microprocessor verification project. The authors v...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2]...
We study the applicability of the logic of Positive Equality with Uninterpreted Functions (PEUF) [2...
RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in mu...
Abstract — In this paper, we propose a verification method for pipelined microprocessors with out-of...
In this paper a practical methodology for formally verifying RISC cores is presented. This methodolo...
Designing a microprocessor is a significant undertaking. Modern RISC processors are no exception. A...
his article describes a formal approach to the specification and verif ication of a microprocessor d...
In microprocessors, achieving an efficient utilization of the execution units is a key factor in imp...
Abstract- As the complexity of high-performance microprocessor increases, functional verification be...
The Verification methodology of modern processor designs is an enormous challenge. As processor desi...
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer S...
The paper presents a sequence of three projects on design and formal verification of pipelined and s...
The paper presents the application of formal verification techniques to a real microprocessor. The d...