This paper presents a novel method to reduce routing congestion during placement stage. The proposed approach is used as a post-processing step in placement. Congestion reduction is based on local improvement on the existing layout. However, the approach has a global view of the congestion over the entire design. It uses integer linear programming (ILP) to formulate the problem of conflicts between multiple congested regions, and performs local improvement according to the solution of the ILP problem. The approximation algorithm of the formulated ILP problem is studied and good approximation bounds are given and proved. Experiments show that the proposed approach can effectively alleviate the congestion of global routing results. The low co...
Congestion is one of the main optimization objectives in global routing. However, the optimization p...
One of the necessary requirements for the placement process is that it should be capable of generati...
By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And...
This paper presents a novel method to reduce routing congestion during placement stage. The proposed...
As technology advances, more and more issues need to be considered in the placement stage, e.g., wir...
This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring ...
This paper presents a new congestion minimization technique for standard cell global placement. The...
We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we sh...
We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we sh...
[[abstract]]An effective congestion-driven placement algorithm that uses initial global routing mode...
Abstract—This paper presents two contributions. The first is an incremental placement algorithm for ...
Abstract—In nanometer-scale VLSI technologies, several interconnect is-sues like routing congestion ...
As the feature size continues scaling down, interconnects become the major contributor of signal del...
For the congestion issue, we found that the existing congestion models will very often over-estimate...
The benefits in reducing traffic congestion of system optimum with respect to user equilibrium traff...
Congestion is one of the main optimization objectives in global routing. However, the optimization p...
One of the necessary requirements for the placement process is that it should be capable of generati...
By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And...
This paper presents a novel method to reduce routing congestion during placement stage. The proposed...
As technology advances, more and more issues need to be considered in the placement stage, e.g., wir...
This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring ...
This paper presents a new congestion minimization technique for standard cell global placement. The...
We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we sh...
We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we sh...
[[abstract]]An effective congestion-driven placement algorithm that uses initial global routing mode...
Abstract—This paper presents two contributions. The first is an incremental placement algorithm for ...
Abstract—In nanometer-scale VLSI technologies, several interconnect is-sues like routing congestion ...
As the feature size continues scaling down, interconnects become the major contributor of signal del...
For the congestion issue, we found that the existing congestion models will very often over-estimate...
The benefits in reducing traffic congestion of system optimum with respect to user equilibrium traff...
Congestion is one of the main optimization objectives in global routing. However, the optimization p...
One of the necessary requirements for the placement process is that it should be capable of generati...
By dividing the packing area into routing tiles, we can give the budget of the buffer insertion. And...