In this paper we address the problem of minimizing buffer storage requirement in constructing rate-optimal compile-time schedules for multi-rate dataflow graphs. We demonstrate that this problem, called the Minimum Buffer Rate-Optimal (MBRO) scheduling problem, can be formulated as a unified linear programming problem. A novel feature of our method is that it tries to minimize the memory requirement while simultaneously maximizing the computation rate. We have constructed an experimental testbed which implements our scheduling algorithm as well as (i) the widely used periodic admissible parallel schedules proposed by Lee and Messerschmitt [12], (ii) the optimal scheduling buffer allocation (OSBA) algorithm of Ning and Gao [15], and (iii) th...
Scheduling data ow graphs onto processors consists of assigning actors to processors, ordering their...
Four scheduling strategies for dataflow graphs onto parallel processors are classified: (1) fully dy...
There has been a proliferation of block-diagram environments for specifying and prototyping DSP sys-...
Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that the node...
Single-Rate Data-Flow (SRDF) graphs, also known as Homogeneous Synchronous Data-Flow (HSDF) graphs o...
: Functional or Control parallelism is an effective way to increase speedups in Multicomputers. Prog...
textMany digital signal processing and real-time streaming systems are modeled using dataflow graphs...
Synchronous dataflow graphs (SDFGs) are widely used to model digital signal processing (DSP) and str...
This paper determines a static scheduling and the minimal size of arc buffers for a given synchronou...
The rapid advances in high-performance computer architecture and compilation techniques provide both...
This paper concerns throughput-constrained parallel execution of synchronous data flow graphs. This ...
Static dataflow graphs are widely used in design of concurrent real-time streaming applications on m...
T his paper addresses trade-offs between the minimization of program memory and data memory requirem...
In the context of digital signal processing, synchronous data flow (SDF) graphs [12] are widely used...
International audienceSymbolic schedulability analysis of dataflow graphs is the process of synthesi...
Scheduling data ow graphs onto processors consists of assigning actors to processors, ordering their...
Four scheduling strategies for dataflow graphs onto parallel processors are classified: (1) fully dy...
There has been a proliferation of block-diagram environments for specifying and prototyping DSP sys-...
Large-grain synchronous dataflow graphs or multi-rate graphs have the distinct feature that the node...
Single-Rate Data-Flow (SRDF) graphs, also known as Homogeneous Synchronous Data-Flow (HSDF) graphs o...
: Functional or Control parallelism is an effective way to increase speedups in Multicomputers. Prog...
textMany digital signal processing and real-time streaming systems are modeled using dataflow graphs...
Synchronous dataflow graphs (SDFGs) are widely used to model digital signal processing (DSP) and str...
This paper determines a static scheduling and the minimal size of arc buffers for a given synchronou...
The rapid advances in high-performance computer architecture and compilation techniques provide both...
This paper concerns throughput-constrained parallel execution of synchronous data flow graphs. This ...
Static dataflow graphs are widely used in design of concurrent real-time streaming applications on m...
T his paper addresses trade-offs between the minimization of program memory and data memory requirem...
In the context of digital signal processing, synchronous data flow (SDF) graphs [12] are widely used...
International audienceSymbolic schedulability analysis of dataflow graphs is the process of synthesi...
Scheduling data ow graphs onto processors consists of assigning actors to processors, ordering their...
Four scheduling strategies for dataflow graphs onto parallel processors are classified: (1) fully dy...
There has been a proliferation of block-diagram environments for specifying and prototyping DSP sys-...