Automatic Performance Analysis on Parallel Computers with SMP Nodes

Parallel computers with SMP nodes provide both multithreading and message passing as their modes of parallel execution. This thesis addresses the complexity of the performance problems that can arise in these systems by formally characterizing the problems in terms of execution patterns that represent situations of inefficient behavior. These patterns are specified as compound events which are input for an automatic analysis process that recognizes and quantifies the inefficient behavior in event traces. Mechanisms that hide the complex relationships within compound-event specifications allow a simple description of complex inefficient behavior on a high level of abstraction