In this paper we present an efficient technique to reduce the power dissipation in a technology mapped CMOS sequential circuit based on logic and structural transformations. The power reduction is achieved by adding sequential redundancies from low switching activity gates to high switching activity gates (targets) such that the switching activities at the output of the targets are significantly reduced. We show that the power reducing transformations result in a circuit that is a valid replacement of the original. The notion of validity used here is that of a delay safe replacement [11, 12]. The potential transformations are found by direct logic implications applied to the circuit netlist. Therefore the complexity of the proposed transfor...
We propose a new power consumption model which accounts for the power consumption at the internal no...
Recently developed methods for power estimation have primarily focused on combinational logic, We pr...
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued lo...
We address the problem of optimizing logic-level sequential circuits for low power. We present a pow...
[[abstract]]In this article we present a new approach to the problem of local logic transformation f...
In this thesis, we address the problem of optimizing sequential logic circuits for low power. We pre...
In this paper we present an efficient technique to reduce the switching activity in a CMOS combinati...
The dissertation addresses several problems in the power optimization and power-delay tradeoffs in d...
This thesis presents techniques for automatically synthesizing VLSI circuits having low power dissip...
This thesis presents techniques for automatically synthesizing VLSI circuits having low power dissip...
[[abstract]]©2002 ACM-In this article we present a new approach to the problem of local logic transf...
In his paper, we address the problem of minimizing the average power dissipation during the technolo...
We propose a logic synthesis system that includes power optimization after technology mapping. Our a...
We present an algorithm that restructures the state transition graph (STG) of a sequential circuit s...
We present an algorithm that restructures the state transition graph (STG) of a sequential circuit s...
We propose a new power consumption model which accounts for the power consumption at the internal no...
Recently developed methods for power estimation have primarily focused on combinational logic, We pr...
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued lo...
We address the problem of optimizing logic-level sequential circuits for low power. We present a pow...
[[abstract]]In this article we present a new approach to the problem of local logic transformation f...
In this thesis, we address the problem of optimizing sequential logic circuits for low power. We pre...
In this paper we present an efficient technique to reduce the switching activity in a CMOS combinati...
The dissertation addresses several problems in the power optimization and power-delay tradeoffs in d...
This thesis presents techniques for automatically synthesizing VLSI circuits having low power dissip...
This thesis presents techniques for automatically synthesizing VLSI circuits having low power dissip...
[[abstract]]©2002 ACM-In this article we present a new approach to the problem of local logic transf...
In his paper, we address the problem of minimizing the average power dissipation during the technolo...
We propose a logic synthesis system that includes power optimization after technology mapping. Our a...
We present an algorithm that restructures the state transition graph (STG) of a sequential circuit s...
We present an algorithm that restructures the state transition graph (STG) of a sequential circuit s...
We propose a new power consumption model which accounts for the power consumption at the internal no...
Recently developed methods for power estimation have primarily focused on combinational logic, We pr...
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued lo...
Add to ORKG