With an increase in the number of transistors on-chip, the complexity of the system also increases. In order to cope with the growing interconnect infrastructure, the "Network on chip (NoC)" concept was introduced. With network methodologies coming on-chip, various characteristics of traditional networks come into play. So far, failures that are common in regular networks were hardly considered onchip; this paper introduces ideas of dynamic routing in the context of NoCs and explains how they could be applied to cope with adverse physical effects of deep sub-micron technology
This paper proposes a look-ahead, fault-tolerant and congestion-aware routing algorithm for Networks...
International audienceNoCs (Networks-on-Chip) are an attractive alternative to communication buses f...
SummaryNetwork-on-Chip has been a growing design paradigm with the rise in Multi-Processor System on...
Abstract — Given the spatial and temporal randomness of soft and permanent errors in the state-of-th...
This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as w...
For most of the history of computing, transistors have been expensive while wires have been cheap. C...
As number of components on the semi-conductor industry is growing at a healthy rate, results in an i...
Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integr...
As silicon features approach the atomic scale, the Networks-on-Chip (NoCs) are becoming more suscept...
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Genera...
In this paper we propose a distributed routing algorithm for networks-on-chip (NoCs) that can dynami...
Downscaled complementary metal-oxide semiconductor (CMOS) technology feature sizes have enabled mass...
Abstract- Networks-on-Chip (NoCs) is an emerging technology and whose accepted solutions cope with t...
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in so...
The aggressive semiconductor technology scaling provides the means for doubling the amount of transi...
This paper proposes a look-ahead, fault-tolerant and congestion-aware routing algorithm for Networks...
International audienceNoCs (Networks-on-Chip) are an attractive alternative to communication buses f...
SummaryNetwork-on-Chip has been a growing design paradigm with the rise in Multi-Processor System on...
Abstract — Given the spatial and temporal randomness of soft and permanent errors in the state-of-th...
This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as w...
For most of the history of computing, transistors have been expensive while wires have been cheap. C...
As number of components on the semi-conductor industry is growing at a healthy rate, results in an i...
Mainstream electronic designs are realized by Systems-on-Chips (SoCs) that push the limits of integr...
As silicon features approach the atomic scale, the Networks-on-Chip (NoCs) are becoming more suscept...
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Genera...
In this paper we propose a distributed routing algorithm for networks-on-chip (NoCs) that can dynami...
Downscaled complementary metal-oxide semiconductor (CMOS) technology feature sizes have enabled mass...
Abstract- Networks-on-Chip (NoCs) is an emerging technology and whose accepted solutions cope with t...
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in so...
The aggressive semiconductor technology scaling provides the means for doubling the amount of transi...
This paper proposes a look-ahead, fault-tolerant and congestion-aware routing algorithm for Networks...
International audienceNoCs (Networks-on-Chip) are an attractive alternative to communication buses f...
SummaryNetwork-on-Chip has been a growing design paradigm with the rise in Multi-Processor System on...