Disassembler using High Level Processor Models

The design of a high performance system requires an integrated environment to simulate and analyze the performance of various design alternatives. In this thesis, we have developed a generic disassembler for an integrated environment where Sim-nML acts as the specification language for processor performance model. The Sim-nML, an extension of nML machine description formalism, is a simple, elegant and powerful language to model machine behavior at instruction level. As part of the thesis work, we have designed an intermediate representation (IR) for processor specification written in Sim-nML language. The IR is simple and facilitates the development of various tools such as assembler, compiler back-end generator, instruction set simulator, trace generator etc. based on the processor specification. A tool, IR-Generator, is developed which takes a processor specification written in Sim-nML language and produces it in the intermediate representation. Further, a Generic Symbolic Disassembler is developed which takes the intermediate representation of a processor and a relocatable binary file in ELF format as input and produces an equivalent program in assembly language of the processor. The disassembler is generic enough to be used for all type of processors