Lower bound estimations of resources at various stages of high-level synthesis are essential to guide synthesis algorithms towards optimal solutions. In this paper we present lower bounds on the number of test resources (i.e. test pattern generators, signature analyzers and CBILBO registers) required to test a synthesized data path using built-in self-test (BIST). The estimations are performed on scheduled data flow graphs and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of test resources to test itself. I. Introduction Estimation of data path resources during high-level synthesis enables a designer to evaluate certain aspects of a ...
Built In Self Test (BIST) has emerged as a promising solution for increasingly fast and dense VLSI c...
This paper addresses the problem of estimating lower bounds on the switching activity in scheduled d...
Fordigital circuits synthesized fiomdata-jlow graphs, this paper presents a method totestthe circuit...
BIST techniques have evolved as cost-effective techniques for digital VLSI testing. A prime concern ...
This paper presents an attempt towards design quality improvement by incorporating of self-testabili...
Area and test time are two major overheads encountered during data path synthesis for BIST. This pap...
Area and test time are two major overheads encountered during data path high level synthesis for BIS...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled da...
Recent research for testable designs has focussed on in-serting test structures by re-arranging an R...
Anew approach to high level synthesis, which simukaneouslyad-dresses testability and resource utiliz...
In this paper, we introduce strong self-testability for data paths at register transfer level (RTL)....
This thesis belongs to the domain of hardware synthesis for testability. The objective of our work w...
This paper presents a method for deriving a BIST specification from the initial specification of dat...
This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test ...
Built In Self Test (BIST) has emerged as a promising solution for increasingly fast and dense VLSI c...
This paper addresses the problem of estimating lower bounds on the switching activity in scheduled d...
Fordigital circuits synthesized fiomdata-jlow graphs, this paper presents a method totestthe circuit...
BIST techniques have evolved as cost-effective techniques for digital VLSI testing. A prime concern ...
This paper presents an attempt towards design quality improvement by incorporating of self-testabili...
Area and test time are two major overheads encountered during data path synthesis for BIST. This pap...
Area and test time are two major overheads encountered during data path high level synthesis for BIS...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled da...
Recent research for testable designs has focussed on in-serting test structures by re-arranging an R...
Anew approach to high level synthesis, which simukaneouslyad-dresses testability and resource utiliz...
In this paper, we introduce strong self-testability for data paths at register transfer level (RTL)....
This thesis belongs to the domain of hardware synthesis for testability. The objective of our work w...
This paper presents a method for deriving a BIST specification from the initial specification of dat...
This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test ...
Built In Self Test (BIST) has emerged as a promising solution for increasingly fast and dense VLSI c...
This paper addresses the problem of estimating lower bounds on the switching activity in scheduled d...
Fordigital circuits synthesized fiomdata-jlow graphs, this paper presents a method totestthe circuit...