Minimal Logic Re-synthesis

Most problems in logic synthesis are computationally hard, and are solved using heuristics. This often makes algorithms un-stable; if the input is changed slightly, the new result of synthesis can be significantly different. A designer can spend much effort hand-optimizing a circuit, so it is desirable to retain as much of this human insight as possible. This motivates the need for incremental synthesis. We propose a re-synthesis algorithm, which allows the designer to designate non-resynthesizable portions of a circuit. We define the concept of minimal change caused by re synthesis, i.e. given a functional change to the circuit, we examine the minimal change to implement this change. For the evaluation of a region for re-synthesis we present techniques for evaluating the "sensitivity" or gain possible with re-synthesis of a set of nodes. We conclude with experimental results and future directions