Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnosing bridging faults using single stuck-at dictionaries was applied only to small circuits, produced large and imprecise diagnoses, and did not take into account the Byzantine Generals Problem for bridging faults. We analyze the original technique and improve it by introducing the concepts of match restriction, match requirement, and failure recovery. Our new technique, which requires no information other than that used by standard stuck-at methods, produces diagnoses that are an order of magnitude smaller than those produced by the original technique and produces many fewer misleading diagnoses than that of traditional stuck-at diagnosis. 1 I...
This paper describes use of a previously proposed test generation program named Jethro to detect the...
AbstractIn VLSI chips the detail circuit implementation is unknown in nearly all cases; only the beh...
ISBN: 0792377311We describe a new method for design error diagnosis in digital circuits that does no...
Physical defects cause behaviors unmodeled by even the best fault simulators, which complicates pred...
A novel algorithm for diagnosing all two-line single bridging faults in combinational circuits is pr...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
If a test set for more complex faults than stuck-at faults is generated, higher defect coverage woul...
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging fa...
A dynamic diagnosis scheme for synchronous sequential circuits is proposed. In contrast with schemes...
UnrestrictedMany studies show that bridging defects are major causes of fabrication failures. A brid...
[[abstract]]© 2003 Institute of Information Science Academia Sinica - Fault diagnosis that predicts ...
[[abstract]]Fault diagnosis that predicts the most likely fault sites in a faulty chip is an importa...
All products in the Very-Large-Scale-Integrated-Circuit (VLSIC) industry go through three major stag...
Aresistive-open defect is an imperfect circuit connection that can be modeled as a defect resistor b...
104 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.Finally, an integrated techni...
This paper describes use of a previously proposed test generation program named Jethro to detect the...
AbstractIn VLSI chips the detail circuit implementation is unknown in nearly all cases; only the beh...
ISBN: 0792377311We describe a new method for design error diagnosis in digital circuits that does no...
Physical defects cause behaviors unmodeled by even the best fault simulators, which complicates pred...
A novel algorithm for diagnosing all two-line single bridging faults in combinational circuits is pr...
The full text of this article is not available on SOAR. WSU users can access the article via IEEE Xp...
If a test set for more complex faults than stuck-at faults is generated, higher defect coverage woul...
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging fa...
A dynamic diagnosis scheme for synchronous sequential circuits is proposed. In contrast with schemes...
UnrestrictedMany studies show that bridging defects are major causes of fabrication failures. A brid...
[[abstract]]© 2003 Institute of Information Science Academia Sinica - Fault diagnosis that predicts ...
[[abstract]]Fault diagnosis that predicts the most likely fault sites in a faulty chip is an importa...
All products in the Very-Large-Scale-Integrated-Circuit (VLSIC) industry go through three major stag...
Aresistive-open defect is an imperfect circuit connection that can be modeled as a defect resistor b...
104 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1997.Finally, an integrated techni...
This paper describes use of a previously proposed test generation program named Jethro to detect the...
AbstractIn VLSI chips the detail circuit implementation is unknown in nearly all cases; only the beh...
ISBN: 0792377311We describe a new method for design error diagnosis in digital circuits that does no...