Hector - A Hierarchically Structured Shared Memory Multiprocessor

This paper describes the architecture of a multiprocessor, called Hector, which exploits current microprocessor technology to produce a machine with good cost/performance tradeoff. A key design feature of Hector is an interconnection backplane that scales well with technology. This is achieved with simple hardware that has short critical paths in logic circuits and short lines in the interconnection network. The result is a system characterized by good performance, reliability and flexibility, which can be realized at a relatively low cost. An important aim of the Hector project is to develop an architecture suitable for construction of a general-purpose multiprocessor, where the cost is directly proportional to the size so that a low-cost entry-level machine is economically feasible, yet is scalable to larger sizes. In order to easily accommodate configurations with varying numbers of processors, Hector has a hierarchical structure. It features small bus sections interconnected by bit-parallel rings. The buses and rings can transfer data independently of each other so that the aggregate bandwidth increases proportionally to the number of these units. Hector is suitable for a wide range of applications. It can be effective for single jobs characterized by many parallel tasks, as well as for concurrent execution of multiple jobs consisting of predominantly serial tasks. That is, it is a machine that can be used effectively to run jobs typical of a Unix environment, as well as highly parallel commercial and scientific applications such as transaction systems, finite element analysis, and computer aided design