The Systolic Reconfigurable Mesh

In this paper, we introduce the Systolic Reconfigurable Mesh (SRM), which combines aspects of the reconfigurable mesh with that of systolic arrays. Every processor controls a local switch that can be reconfigured during every clock cycle in order to control the physical connections between its four bi-directional bus lines. Data is input from one side of the systolic reconfigurable mesh and output from another side, one column per unit time. Efficient algorithms are presented for intermediate-level vision tasks including histograming, connectivity, convexity and proximity. 1 Introduction The reconfigurable mesh was originally proposed as a massively parallel computing model in the mid-1980s [6, 4, 8]. A review of the algorithmic literature [7] suggests that the major emphasis has been on i) fundamental problems, including sorting and arithmetic, ii) problems involving regularly structured data, such as matrices and images, in areas such as graph theory and image processing, and iii) ..