Extraction, Simulation And IDDQ Test Generation For Efficient Bridging Fault Detection in Digital VLSI Circuits

In this paper we give an overview of recent work in extraction, simulation, and IDDQ test generation for bridging faults (BFs) in digital VLSI circuits. We then show how these techniques can be applied in a hybrid (logic+IDDQ) testing strategy for efficient BF detection in sequential circuits. In this strategy, logic and IDDQ tests are performed in that order. Realistic BFs are first extracted from circuit layouts. Then a voltage-based BF simulation is performed on the extracted BFs to filter out those BFs that can be detected by logic testing. IDDQ test generation is then performed targeting the remaining BFs. This hybrid testing strategy shows superior fault coverage with very short IDDQ test sets. In addition, the test generation time for this approach is significantly shorter than that a recently proposed approach. I. INTRODUCTION Due to the high integration density of VLSI circuits, bridging faults (a physical defect that form a faulty resistive short between two conducting nets..