Hardware Implementations of Kohonen's Selforganizing Feature Map

In this paper we present a hardware realization of Kohonen's selforganizing feature map as a neural coprocessor connected to a personal computer (PC). We compare two concepts for this coprocessor, a vector-component-serial and processing-element-parallel array processor and a vector-component-parallel and processing-element-serial vector processor. Finally we give an overview about the whole system integrating the neural coprocessor with its different components and their tasks. 1 Introduction Large CPU-times for training large data sets to neural networks constitute a serious obstacle for practical applications of neural networks, especially software simulations on MIMD-computers, e.g. transputer networks [11], or on SIMD-computers (we are using MasPar with the language Parallaxis [1]), bring up the performance. For some general concepts which have many applications specialized hardware may further improve the performance. One of these concepts is the selforganizing feature map which..