Layout Extraction of 3D Models for Interconnect and Substrate Parasitics

this paper we present methods to model these effects directly from the layout of a circuit. All methods are implemented in a layout-to-circuit extractor [2]. The input of the extractor is the layout and a technology file. The output is a netlist which can be simulated with Spice, after appropriate stimuli have been added. Conventional methods are usually heuristic in nature or are based on complete numerical field solutions. Thus they are unsuitable for geometrically complex and/or large designs. Although our approach is based on numerical methods (Finite Element for interconnect resistances and Boundary Element for capacitances and substrate noise), it directly yields equivalent electrical networks without solving a field problem. E.g., the inverse of the Boundary Element influence matrix can be interpreted as a capacitance network between all elements, independent of the applied potentials. In combination with efficient network reduction techniques this yields accurate models for the parasitics [3]. Figure 1 shows a layout of an NMOS modulo-2 circuit. It is driven such that it acts as an AND gate for the inputs a and non-b. Figure 2 shows the input sequences and the Spice results for the circuit with and without an extracted RC model for the interconnect. The interconnect has a clear influence on the behaviour, even such that the circuit is malfunctioning at this speed. Table 1 shows some characteristic data obtained from Spice simulations of a CMOS static RAM cell (Figure 3). Clearly the interconnect parasitics (mainly the capacitances) have an adverse effect on the performance of the cell. Figure 4 shows the layout of a metallization dummy structure (open) for HF admittance parameter measurements for MOSFET characterization. The bottom left bondpad is connected thro..