Total Dose and Single Event Effects (SEE) in a 0.25μm CMOS Technology

Individual transistors, resistors and shift registers have been designed using radiation tolerant layout practices in a commercial quarter micron process. A modelling effort has led to a satisfactory formulation for the effective aspect ratio of the enclosed transistors used in these layout practices. All devices have been tested up to a total dose of 30Mrad(SiO 2 ). The threshold voltage shift after irradiation and annealing was about +45mV for NMOS and-55mV for PMOS transistors, no leakage current appeared, and the mobility degradation was below 6%. The value of resistors increased by less than 10%. Noise measurements made on transistors with W=2mm and L varying between 0.36 and 0.64Pm revealed a corner noise frequency of about 200kHz for the NMOS and 12kHz for the PMOS. Irradiation up to 30Mrad(SiO 2 ) did not significantly affect the noise performance. The shift registers continuously operated at 1.25MHz during the irradiation, and no error was detected in the pattern propagation...