D CMOS SOI for High Performance Computing

This paper addresses three topics : First, a new three-dimensional CMOS-SOI on SOI technology is presented, then design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs. In this technology the P-channel devices are stacked over the N-channel ones. All gates are 100nm length. New design constraints are introduced. Consequently, new design methodologies have to be developed in order to fully take advantage of the outstanding features of 3D integration like for example the reduced length of interconnections. A 16x16 bit multiplier was designed in this technology. Comparative results between 2D and 3D integration are given here in terms of energy consumption, delay and area INTRODUCTION In this paper a new three dimensional 100nm channel length CMOS-SOI technology is presented. It consists of two layers of transistors - Silicon On Insulator on Silicon On Insulator [1]. This technology is being developed at the IMS (Institute f..