Clock-Routing Driven Layout Methodology for Semi-Synchronous Circuit Design

The most expensive part in modern VLSIs is the clockdistribution network where the clock is assumed to be distributed periodically and simultaneously. While, in the semi-synchronous system, the clock is assumed to be distributed periodically, but not necessarily simultaneously. In this framework, we propose a new design methodology which maximizes the performance of a circuit subject to the minimum cost clock-distribution network. The clock-delay map is calculated in advance and then the circuit placement procedure maximizes the performance according to it. This methodology reduces the clock-distribution cost significantly. The experiments show that the performance of a circuit obtained by our methodology is comparable with that of the complete-synchronous circuit in most cases. 1 Introduction In layout synthesis, distribution of the clock is critical to the performance of sequential circuits. In the complete-synchronous system, the clock is assumed to be distributed periodically and..