Interprocedural Analysis for Loop Scheduling and Data Allocation

In order to reduce remote memory accesses on CC-NUMA multiprocessors, we present an interprocedural analysis to support static loop scheduling and data allocation. Given a parallelized program, the compiler constructs graphs which represent globally and interprocedurally the remote reference penalties associated with different choices for loop scheduling and data allocation. After deriving an optimal solution according to those graphs, the compiler generates data allocation directives and schedules DOALL loops. Experiments indicate that the proposed compiler scheme is efficient and simulation results show good performance of the parallel code. 1 Introduction Executing independent loop iterations on multiple processors is an important approach to improving program execution speed. A loop which contains sufficient parallelism among its iterations can be parallelized either manually by a programmer or, in many cases, automatically by a compiler. Once a loop is transformed into a parallel..