JUMP-1 is currently under development by seven Japanese universities to establish techniques of an efficient distributed shared memory on a massively parallel processor. It provides a memory coherency control scheme called the hierarchical bit-map directory to achieve cost effective and high performance management of the cache memory. Messages for maintaining cache coherency are transferred through a fat tree on the RDT(Recursive Diagonal Torus) interconnection network. In this report, we discuss on the scheme and examine its performance. The configuration of the RDT router chip is also discussed. 1 Introduction JUMP-1 is a massively parallel processor prototype developed by collaboration between 7 Japanese universities[4]. The major goal ...
[[abstract]]An optimization scheme for a directory-based cache coherence protocol for multistage int...
As microprocessors become faster and demand more bandwidth the already limited scalability of a shar...
Cache coherence and synchronization between processors have been two critical issues in designing a ...
Design Outline The RDT network Router chip is a versatile router for the massively parallel computer...
Cache coherence problem is a major concern in the design of shared-memory multiprocessors. As the nu...
In this thesis we propose and evaluate an architecture to build large scale distributed shared memor...
This paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchi...
Multiprocessors with shared memory are considered more general and easier to program than message-pa...
A b s t r a c t- This paper proposes a distributed directory cache coherence protocol and compares t...
This paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchi...
We describe the design of a directory-based shared memory architecture on a hierarchical network of ...
We describe the design of a directory-based shared memory architecture on a hierarchical network of ...
The long latencies introduced by remote accesses in a large multiprocessor can be hidden by caching....
[[abstract]]A method of maintaining cache coherency in a shared memory multiprocessor system having ...
The Data Diffusion Machine (DDM) is a scalable shared memory multiprocessor in which the location of...
[[abstract]]An optimization scheme for a directory-based cache coherence protocol for multistage int...
As microprocessors become faster and demand more bandwidth the already limited scalability of a shar...
Cache coherence and synchronization between processors have been two critical issues in designing a ...
Design Outline The RDT network Router chip is a versatile router for the massively parallel computer...
Cache coherence problem is a major concern in the design of shared-memory multiprocessors. As the nu...
In this thesis we propose and evaluate an architecture to build large scale distributed shared memor...
This paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchi...
Multiprocessors with shared memory are considered more general and easier to program than message-pa...
A b s t r a c t- This paper proposes a distributed directory cache coherence protocol and compares t...
This paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchi...
We describe the design of a directory-based shared memory architecture on a hierarchical network of ...
We describe the design of a directory-based shared memory architecture on a hierarchical network of ...
The long latencies introduced by remote accesses in a large multiprocessor can be hidden by caching....
[[abstract]]A method of maintaining cache coherency in a shared memory multiprocessor system having ...
The Data Diffusion Machine (DDM) is a scalable shared memory multiprocessor in which the location of...
[[abstract]]An optimization scheme for a directory-based cache coherence protocol for multistage int...
As microprocessors become faster and demand more bandwidth the already limited scalability of a shar...
Cache coherence and synchronization between processors have been two critical issues in designing a ...