Concurrent Analysis Techniques for Data Path Timing Optimization

Conventional High-level Synthesis techniques create an interconnection structure before physical design. Following physical design, connection delays and special requirements may cause the structure to fail timing or performance constraints. Alterations to this structure are often limited since it was created either after or during the binding and scheduling tasks. In this paper we present a set of techniques which analyze the timing trade-offs associated with the position-specific interconnection network given the freedom of high-level binding and rescheduling changes. 3. Problem Specification In this work, the automata based data-path model introduced in [7] is utilized to implicitly execute a series of data flows on a detailed RTL data path. Given the additions of a floorplan, a set of alternative interconnection networks, and a set of timing ranges, the automata will produce a timed output sequence as well as characterize the timing behavior of the "care paths" for each element ..