This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification without further modifications. However, to improve manufacturability, we introduce a concept called even wire distribution, a key element of the SURF physical design tool. To alleviate congestion, we first move vias and wires towards less dense areas in a manner which preserves the existing wiring paths. Depending on the locally available area, we then increase wire spacing to reduce defect sensitivity, without changing the area of the design. Carafe, an inductive fault analysis tool is used to evaluate the new layout. 1.0 Introduction Design for manufacturability (DFM...
One of the vital phases in the design flow of electronic artifacts is the phase called physical desi...
Abstract — This article describes an algorithm for curvilinear detailed routing. We significantly im...
The impact of spot defects on the susceptibility for electrical failure of a net is analyzed. Based ...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
Several yield and reliability enhancement techniques have been proposed for the compaction, routing ...
Traditionally, the goal of channel routing algorithms is to route the nets with as few tracks as pos...
Increasing challenges arise with each new semiconductor technology node, especially in advanced node...
Ph.D. University of Hawaii at Manoa 2012.Includes bibliographical references.As the minimum feature ...
chemical–mechanical polishing (CMP) topography variation control becomes crucial for manufacturing c...
Unlike traditional design rule checks (DRCs), which have a clear pass or fail definition, yield issu...
9/5/2014For modern deep nano-scale integrated circuit manufacturers, constructing large and complex ...
Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catas...
Most existing performance-driven and clock routing algorithms construct optimal routing topology for...
As we increasingly use advanced technology nodes to design integrated circuits (ICs), physical desig...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
One of the vital phases in the design flow of electronic artifacts is the phase called physical desi...
Abstract — This article describes an algorithm for curvilinear detailed routing. We significantly im...
The impact of spot defects on the susceptibility for electrical failure of a net is analyzed. Based ...
This paper presents a unique approach to improve yield given a routed layout. Currently after routin...
Several yield and reliability enhancement techniques have been proposed for the compaction, routing ...
Traditionally, the goal of channel routing algorithms is to route the nets with as few tracks as pos...
Increasing challenges arise with each new semiconductor technology node, especially in advanced node...
Ph.D. University of Hawaii at Manoa 2012.Includes bibliographical references.As the minimum feature ...
chemical–mechanical polishing (CMP) topography variation control becomes crucial for manufacturing c...
Unlike traditional design rule checks (DRCs), which have a clear pass or fail definition, yield issu...
9/5/2014For modern deep nano-scale integrated circuit manufacturers, constructing large and complex ...
Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catas...
Most existing performance-driven and clock routing algorithms construct optimal routing topology for...
As we increasingly use advanced technology nodes to design integrated circuits (ICs), physical desig...
In VLSI physical design, the routing task consists of using over-the-cell metal wires to connect pin...
One of the vital phases in the design flow of electronic artifacts is the phase called physical desi...
Abstract — This article describes an algorithm for curvilinear detailed routing. We significantly im...
The impact of spot defects on the susceptibility for electrical failure of a net is analyzed. Based ...