ASIC Yield Estimation At Early Design Cycle

This paper describes an ASIC yield model based on the CMOS bridge fault model. The model predicts defect sensitive area early in the design cycle as a function of number of gates and nets. 1 INTRODUCTION The semiconductor industry has continuously been looking for ways to improve yield and reduce manufacturing cost. Although chip yield is the key element of IC manufacturing economics, the estimation of yield early in the design cycle still remains a challenging problem. Early prediction of yield is important for costing and capacity estimations. An early warning of low yield may trigger design modifications while there is still time, thus meeting the cost and quality goals. Previous research proposed various IC yield models, and Cunningham [1] summarized popular IC yield models. Popular yield models include Poisson, Murphy, Seeds, Moore, Price, and negative binomial. Table 1 summarizes chip yield models. All the above yield models are function of defect spectrum(defect density) D 0 a..