Triggering And Event Building Results Using The C104 Packet Routing Chip

Introduction The bandwidth and connectivity requirements of trigger and data acquisition systems for future HEP experiments at the CERN LHC and HERA-B at DESY, highlight the limitations in scaling embedded multi-processor bus based systems. The prominently featured alternative in the proposed systems is large switching networks. The performance of large switching fabrics has been studied within the context of message passing multi-processing computers 1 . However, these studies were based on telecommunications traffic patterns which differs to those expected in the trigger systems of HEP experiments. In the latter, switching fabrics will be required to connect N sources to M destinations, where M and N are of order 250. The traffic pattern will be `bursty' and have different characteristics for level II and III triggers. The modeling of large switching fabrics under such traffic patterns is being performed by several groups 2;3;