This paper presents an improved measure for the dynamic functionality of a logic circuit, called delay fault probability (DFP). The new measure reflects both the nominal delay of the paths and the fact that only few paths are critical for path delay fault testing. An efficient distributed algorithm for computing DFP is presented. The experimental results show that, in contrast to DFP, the conventional fault coverage is an inadequate criterion to assure the dynamic functionality of a circuit
Circuits are tested for both functionality and performance. As opposed to circuits with large delay ...
We investigate two strategies to guarantee temporal correctness of a combinational circuit. We first...
Circuits are tested for both functionality and performance. As opposed to circuits with large delay ...
[[abstract]]Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we e...
We propose a coverage metric and a two-pass test generation method for path delay faults in combinat...
We propose a coverage metric and a two-pass test generation method for path delay faults in combinat...
Abstract The implementation of a system for analyzing circuits with respect to their path-delay faul...
Path selection and generating tests for small delay faults is an important issue in the delay fault ...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diag...
Technology scaling and manufacturing process affect the performance of digital circuits, making them...
As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing...
[[abstract]]This paper defines a new diagnosis problem for diagnosing delay defects based upon stati...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
Circuits are tested for both functionality and performance. As opposed to circuits with large delay ...
We investigate two strategies to guarantee temporal correctness of a combinational circuit. We first...
Circuits are tested for both functionality and performance. As opposed to circuits with large delay ...
[[abstract]]Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we e...
We propose a coverage metric and a two-pass test generation method for path delay faults in combinat...
We propose a coverage metric and a two-pass test generation method for path delay faults in combinat...
Abstract The implementation of a system for analyzing circuits with respect to their path-delay faul...
Path selection and generating tests for small delay faults is an important issue in the delay fault ...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], whic...
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diag...
Technology scaling and manufacturing process affect the performance of digital circuits, making them...
As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing...
[[abstract]]This paper defines a new diagnosis problem for diagnosing delay defects based upon stati...
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructi...
Circuits are tested for both functionality and performance. As opposed to circuits with large delay ...
We investigate two strategies to guarantee temporal correctness of a combinational circuit. We first...
Circuits are tested for both functionality and performance. As opposed to circuits with large delay ...