We present a decision method for automatic verification of a nontrivial class of systolic circuits. A formal model for systolic circuits, and a formal definition of systolic circuit verification are provided. Using this model, we give a decision method for verification of a class of circuits, in which the cell operations of the circuits are regarded as uninterpreted function symbols. If a circuit is verified in this manner then the circuit is correctly implemented with respect to its specification regardless of the particular interpretation of the cell operations. Finally we show that simple generalizations of the class lead to undecidable verification problems. Examples of circuits which can be verified automatically by our method include ...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
We pressent an approach to reasoning about the functional behaviour of circuits. The approach begin...
Abstract—Formal methods have been advocated for the verification of digital designs where correctnes...
Systolic circuits have drawn considerable attention as a means of implementing parallel algorithms i...
We describe a new tautology checking algorithm that can determine whether a logic circuit correctly ...
this paper we survey some state-of-the-art techniques used to perform automatic verification of comb...
Journal ArticleWe illustrate that the verification of systolic architectures can be carried out usin...
An approach is described to the specification and verification of digital systems implemented wholly...
This paper proposes a verification flow for mixed-signal circuits. The presented flow is based on 'b...
The dissertation describes a practically proven, particularly efficient approach for the verificatio...
A logic simulator can prove the correctness of a digital circuit when it can be shown that only circ...
Abstract. There is a large class of circuits (including pipeline and outof-order execution component...
Nowadays, logic synthesis tools are widely used to optimize and implement digital systems. Verifying...
[[abstract]]The authors have previously (1990) developed a new formalism, called systolic temporal a...
Many aspects of digital circuit operation can be efficiently verified by simulating circuit operat...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
We pressent an approach to reasoning about the functional behaviour of circuits. The approach begin...
Abstract—Formal methods have been advocated for the verification of digital designs where correctnes...
Systolic circuits have drawn considerable attention as a means of implementing parallel algorithms i...
We describe a new tautology checking algorithm that can determine whether a logic circuit correctly ...
this paper we survey some state-of-the-art techniques used to perform automatic verification of comb...
Journal ArticleWe illustrate that the verification of systolic architectures can be carried out usin...
An approach is described to the specification and verification of digital systems implemented wholly...
This paper proposes a verification flow for mixed-signal circuits. The presented flow is based on 'b...
The dissertation describes a practically proven, particularly efficient approach for the verificatio...
A logic simulator can prove the correctness of a digital circuit when it can be shown that only circ...
Abstract. There is a large class of circuits (including pipeline and outof-order execution component...
Nowadays, logic synthesis tools are widely used to optimize and implement digital systems. Verifying...
[[abstract]]The authors have previously (1990) developed a new formalism, called systolic temporal a...
Many aspects of digital circuit operation can be efficiently verified by simulating circuit operat...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
We pressent an approach to reasoning about the functional behaviour of circuits. The approach begin...
Abstract—Formal methods have been advocated for the verification of digital designs where correctnes...