A Survey of Formal Hardware Verification Tools Developed in Europe

This article gives a survey on formal hardware verification tools developed in Europe. It describes the main objectives and domains of application of the formal methods for the verification of electronic systems. Further, it gives an overview of the formal methods used in the most significant European research in this domain. It attempts to introduce some classification scheme for the existing commercial or prototype tools, which is based on the different verification aspects: type of the circuit to verify, abstraction level, verification objective, mathematical model, formal proof technique, input formalism, diagnostic method incorporated and the others. The most significant features of the methods and tools are summarized, and some advantages and drawbacks are discussed. Finally, some conclusions concerning the possible future trends in development are drawn. 1. Background and objectives of the presented work. Traditionally, the verification of the design correctness is performed b..