Add to ORKGIn this paper we present a Low Voltage Differential Current Switch Logic (LVDCSL) gate which is capable of achieving high performance for large fan-in gates. High fan-in is enabled by allowing large stacked NMOS tree heights using a pre-discharged NMOS tree, at the same time the power penalty of an increased number of internal nodes in the gate is mitigated by restricting internal node voltage swings. It is topologically a Cascode Voltage Switch Logic Gate with a cross-coupled inverter based load. However, unlike other DCVS gates with cross-coupled inverters, it is fairly robust and relatively insensitive to load imbalances at the output. The salient features of this low-voltage DCSL family are: high speed for high fan-in large stack height...
Abstract—This article presents a power-efficient low-voltage differential signaling (LVDS) output dr...
Abstract — High speed and small area are the main advantages of the dynamic logic for digital circui...
Abstract—This paper proposes a new transistor topology to design gates required by Null Convention L...
We present a new logic family, Differential Current Switch Logic (DCSL) for implementing clocked CMO...
This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch L...
Abstract—The limited switch dynamic logic (LSDL) family is a hybrid of dynamic and static logic whic...
In this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) whi...
[[abstract]]A CMOS differential logic, called the latched CMOS differential logic (LCDL), is propose...
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introduc...
With the continued scaling of CMOS VLSI, power dissipation of logic circuits has increasingly come t...
Cascode voltage switch (CVS) logic is a CMOS circuit technique which has potential advantages over c...
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) ...
The objective vividly defines a new low-power and high-speed logic family; named Self Resetting Logi...
Differential Cascode Voltage Switch (DCVS) logic is a dynamic logic family that has a number of desi...
Abstract—This article presents a power-efficient low-voltage differential signaling (LVDS) output dr...
Abstract — High speed and small area are the main advantages of the dynamic logic for digital circui...
Abstract—This paper proposes a new transistor topology to design gates required by Null Convention L...
We present a new logic family, Differential Current Switch Logic (DCSL) for implementing clocked CMO...
This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch L...
Abstract—The limited switch dynamic logic (LSDL) family is a hybrid of dynamic and static logic whic...
In this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) whi...
[[abstract]]A CMOS differential logic, called the latched CMOS differential logic (LCDL), is propose...
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introduc...
With the continued scaling of CMOS VLSI, power dissipation of logic circuits has increasingly come t...
Cascode voltage switch (CVS) logic is a CMOS circuit technique which has potential advantages over c...
The Critical Voltage Transition Logic (CVTL) was proposed by in [1] [2]. The concept of the design ...
In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) ...
The objective vividly defines a new low-power and high-speed logic family; named Self Resetting Logi...
Differential Cascode Voltage Switch (DCVS) logic is a dynamic logic family that has a number of desi...
Abstract—This article presents a power-efficient low-voltage differential signaling (LVDS) output dr...
Abstract — High speed and small area are the main advantages of the dynamic logic for digital circui...
Abstract—This paper proposes a new transistor topology to design gates required by Null Convention L...