. In this paper, we present methods for eliminating higher-order quantifiers in proof goals arising in the verification of digital circuits. For the description of the circuits, a subset of higher-order logic called hardware formulae is used which is sufficient for describing hardware specifications and implementations at register transfer level. Real circuits can be dealt with as well as abstract (generic) circuits. In case of real circuits, it is formally proved, that the presented transformations result in decidable formulae, such that full automation is achieved for them. Verification goals of abstract circuits can be transformed by the presented methods into goals of logics weaker than higher-order logic, e.g. (temporal) propositional ...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
Deep datapath and algorithm complexity have made the verification of floating-point units a very har...
. In this article we present a structured approach to formal hardware verification by modelling circ...
Abstract. In this article we present a structured approach to formal hardware verification by modeli...
this paper, a verification method is presented which combines the advantages of deduction style proo...
Ascertaining correctness of digital hardware designs through simulation does not scale-up for large ...
Ascertaining correctness of digital hardware designs through simulation does not scale-up for large ...
) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design...
The aim of this thesis is to investigate the integration of hardware description lamguaages (HDLs) a...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
Abstract. We have developed a verification framework that combines deductive reasoning, general purp...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
ion Mechanisms for Hardware Verification Thomas F. Melham University of Cambridge Computer Laborat...
We develop quantifier elimination procedures for a fragment of higher order logic arising from the f...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
Deep datapath and algorithm complexity have made the verification of floating-point units a very har...
. In this article we present a structured approach to formal hardware verification by modelling circ...
Abstract. In this article we present a structured approach to formal hardware verification by modeli...
this paper, a verification method is presented which combines the advantages of deduction style proo...
Ascertaining correctness of digital hardware designs through simulation does not scale-up for large ...
Ascertaining correctness of digital hardware designs through simulation does not scale-up for large ...
) Ramayya Kumar, Thomas Kropf, Klaus Schneider University of Karlsruhe, Institute of Computer Design...
The aim of this thesis is to investigate the integration of hardware description lamguaages (HDLs) a...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
Abstract. We have developed a verification framework that combines deductive reasoning, general purp...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
ion Mechanisms for Hardware Verification Thomas F. Melham University of Cambridge Computer Laborat...
We develop quantifier elimination procedures for a fragment of higher order logic arising from the f...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
We present a new approach to hardware verification based on describing circuits in Monadic Second-or...
Deep datapath and algorithm complexity have made the verification of floating-point units a very har...