Constraints Space Management for the Layout of Analog IC's

An automated technique to narrow down the number of constraints in analog layout is described. The set of most important layout constraints is determined, discarding unnecessary constraints. The method is based on principal component analysis of the sensitivity matrix. Experimental results suggest the effectiveness of the method with respect to parasitic estimation and to the error margin. The results are compared with human designers' art in hand-crafted constraints confinement. 1. Introduction High performance analog IC layout is the more laborious part of an IC design task. The main problems in today's deep-submicron layout design are stray parasitics, signal integrity and crosstalk, which forces the designers to adopt special strategies for state-of-the-art analog design. Analog and mixed design are facing the problems of low-power low-voltage requirements, which further complicate analog layout. This generally results in costly iterations between behavioral and physical design, i..