A synthesis procedure for asynchronous control circuits from a high level specification, signal transition graph (STG), is described. In this paper, we propose some syntactic constraints on STG to guarantee hazard-free implementation. We have introduced a global persistency concept in order to establish the relationship between the persistency concept introduced by Chu [2] (which we call local persistency) and the consistent state coding (CSC). The STG syntactic constraints required to compute the input set of a signal are identified. We analyze all hazards under both single and multiple input change conditions and propose necessary changes to the net contraction and logic synthesis procedures. The proposed changes are guaranteed to generat...
Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) ...
Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) ...
This paper develops a theoretical framework for the hazard-free gate-level implementation of speed-i...
A synthesis technique for asynchronous sequential control circuits from a high level specification, ...
Methods for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) have commonl...
Methods for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) have commonl...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asyn...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal...
Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour...
Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour...
This paper presents a new method to synthesize timed asyn-chronous circuits directly from the specif...
This work investigates testability of asynchronous circuits and its relation with signal transition ...
The synthesis of asynchronous circuits is inherently complex for two different aspects. Firstly, the...
Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) ...
Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) ...
This paper develops a theoretical framework for the hazard-free gate-level implementation of speed-i...
A synthesis technique for asynchronous sequential control circuits from a high level specification, ...
Methods for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) have commonl...
Methods for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) have commonl...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asyn...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal...
Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour...
Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour...
This paper presents a new method to synthesize timed asyn-chronous circuits directly from the specif...
This work investigates testability of asynchronous circuits and its relation with signal transition ...
The synthesis of asynchronous circuits is inherently complex for two different aspects. Firstly, the...
Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) ...
Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) ...
This paper develops a theoretical framework for the hazard-free gate-level implementation of speed-i...