The Design of a Hierarchical Processors-and-Memory Architecture for High Performance Computing

Introduction Applications are an important driving force behind the emergence of new machine architectures and organizations. In response to the needs of large, computeintensive applications, heterogeneous architectures are one viable alternative. Several heterogeneous systems [AnPo 91], [BaWh 89], [Be et al. 96], [BeFo 96], [MeAl 90], and [Mo et al. 96] were shown to be able to achieve better performance than homogeneous systems and to offer a more cost-efficient computing environment. Given that future applications are expected to require in excess of 100 Teraops computing speed [St et. al 95], economical and financial considerations become crucial issues in the design of new systems that can achieve these speeds. In order to satisfy the computational demands of current and future applications, a heterogeneous system organized as a hierarchy of processors-andmemory subsystems (HPAM) is proposed. HPAM was previously introduced in [Be et al. 96] and [BeFo 96]. This extended a