A 700 Mbps/pin CMOS Signalling Interface Using Current Integrating Receivers

A high speed CMOS signalling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes 1-V push-pull drivers, a Delay Line PLL and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 µm CMOS technology achieve transfer rates of 740 Mbits/sec/pin operating from a 3.3-V supply with a bit error rate of less than 10 -14