System-Level Modeling and Verification: a Comprehensive Design Methodology

* Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and verification at system-level. 1. Introduction The boundaries of hardware description are rapidly migrating towards higher and higher levels of abstraction. Until not long ago, designers mainly worked at register-transfer level, whereas new activities at system-level are now emerging. Systems are conceived before partitioning between hardware and software realization takes place, so that many alternatives can be explored before defining the final hardware/software architecture. Among the most relevant activities at system-level, we list specification description and validation, and system description and verification. Most efforts in..