Bus Utilization Analysis of Multithreaded Shared-Bus Multiprocessors: Initial Results

A shared-bus shared-memory multiprocessor based on multithreaded CPUs is evaluated against different solutions for cache and coherence protocols. Multithreaded architectures have been intensively studied for DSM multiprocessors, where memory latencies are a major factor in limiting performance. They can be interesting also for bus-based multiprocessors, since processor speed are increasing at a much faster rate than memory. In these systems, not only pure parallel workloads, but also workloads consting of both parallel and sequential applications are the typical object of user demand for processing power. The aim of this work is to investigate the relations among workloads of this kind, multithreaded processors, sharedbus architecture, coherence schemes, and thereby the consequences on performance. We have used an enhanced trace-driven approach that takes into consideration both user and kernel references. Results show that multithreaded processors can play an effective role in boostin..