Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory have increased. Unfortunately, memory systems have not kept pace. Even hierarchical cache structures are ineffective if programs do not exhibit cache locality. Because of this compilers need to be concerned not only with finding ILP to utilize machine resources effectively, but also with ensuring that the resulting code has a high degree of cache locality. One compiler transformation that is essential for a compiler to meet the above objectives is unroll-and-jam, or outer-loop unrolling. Previous work either has used a dependence-based model [7] to compute unroll amou...
The development of embedded applications typically faces memory and/or execution time con-straints. ...
This thesis investigates compiler algorithms to transform program and data to utilize efficiently th...
Over the past 20 years, increases in processor speed have dramatically outstripped performance incre...
ii The high performance of today’s microprocessors is achieved mainly by fast, multipleissuing hardw...
Compilers base many critical decisions on abstracted architectural models. While recent research has...
In order to deliver the promise of MooreÂs Law to the enduser, compilers must make decisions that ar...
We introduce Approximate Unrolling, a loop optimization that reduces execution time and energy consu...
This work was also published as a Rice University thesis/dissertation: http://hdl.handle.net/1911/16...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
It is well-known that, to optimize a program for speed-up, efforts should be focused on the regions ...
Journal PaperCurrent microprocessors incorporate techniques to exploit instruction-level parallelism...
International audienceThis article studies an important open problem in backend compilation regardin...
International audienceWe address the problem of generating compact code from software pipelined loop...
We address the problem of generating compact code from software pipelined loops. Although software p...
International audienceModulo Variable Expansion (MVE) [1] used with soft- ware pipelining (SWP) may ...
The development of embedded applications typically faces memory and/or execution time con-straints. ...
This thesis investigates compiler algorithms to transform program and data to utilize efficiently th...
Over the past 20 years, increases in processor speed have dramatically outstripped performance incre...
ii The high performance of today’s microprocessors is achieved mainly by fast, multipleissuing hardw...
Compilers base many critical decisions on abstracted architectural models. While recent research has...
In order to deliver the promise of MooreÂs Law to the enduser, compilers must make decisions that ar...
We introduce Approximate Unrolling, a loop optimization that reduces execution time and energy consu...
This work was also published as a Rice University thesis/dissertation: http://hdl.handle.net/1911/16...
The trend in high-performance microprocessor design is toward increasing computational power on the ...
It is well-known that, to optimize a program for speed-up, efforts should be focused on the regions ...
Journal PaperCurrent microprocessors incorporate techniques to exploit instruction-level parallelism...
International audienceThis article studies an important open problem in backend compilation regardin...
International audienceWe address the problem of generating compact code from software pipelined loop...
We address the problem of generating compact code from software pipelined loops. Although software p...
International audienceModulo Variable Expansion (MVE) [1] used with soft- ware pipelining (SWP) may ...
The development of embedded applications typically faces memory and/or execution time con-straints. ...
This thesis investigates compiler algorithms to transform program and data to utilize efficiently th...
Over the past 20 years, increases in processor speed have dramatically outstripped performance incre...