Synthesis of Timed Circuits using BDDs

This paper presents a tool which synthesizes timed circuits from reduced state graphs. Using timing information to reduce state graphs can lead to significantly smaller and faster circuits. The tool uses implicit techniques (binary decision diagrams) to represent these graphs. This allows us to synthesize larger, more complex systems which may be intractable with an explicit representation. We are also able to create a parameterized family of solutions, facilitating technology mapping. 1. Introduction Asynchronous design has been gaining in popularity in recent years [5, 6, 8, 14]. Increasing clock speeds and larger ICs make it ever more difficult to maintain a globally synchronous environment. Asynchronous circuits eliminate these difficulties by removing clocks and using independent handshaking protocols. We work with a class of asynchronous circuits known as timed circuits, which use explicit timing information to optimize the implementation[10]. Using timing information makes it p..