Improving Memory Access Performance Using a Code Coalescing Unit

High clock frequencies combined with deep pipelining employed by many of the state-ofthe -art processors have forced cache hit accesses to be multi-cycle operations. For many programs, untolerated load latencies account for a significant portion of total execution time. In this paper, we present a mechanism called the Code Coalescing Unit (CCU) that can identify and eliminate at run-time several load operations. The multi-cycle load operations are converted to register read operations with zero latency. Our approach works by using a special buffer called the Store Register Rename Buffer (SRRB), to store the addresses and data for the stores. Subsequent loads for the data are avoided by the CCU by appropriate micro-architectural register renaming. The load operations are converted to register read accesses avoiding costly address translation and cache access which typically takes two or three cycles. The SRRB is used as an extension to the regular register file. The SRRB is similar in s..